Dynamic random access memories (DRAMs) provide fast and high-volume memories for data access in computer and mobile computer systems. Power consumption has been a concern about DRAMs because DRAMs require data refreshing periodically. One conventional design for DRAMs includes introducing a deep power down (DPD) mode. However, in the DPD mode, data stored in a DRAM may be destroyed. In addition, it may need a long period of time, e.g. 500 us, to recover access to the DRAM from a DPD mode.
One conventional approach for preventing data loss in DRAMs in a DPD mode is using static random access memories (SRAMs) to hold data while in a DPD mode. However, adding SRAM cells may incur large area overhead and increase response time for data access. Another conventional approach for reducing power consumption is utilizing a self-refresh mode to maintain data and provide data access to DRAMs within about 100 ns from the self-refresh mode. However, such a self-refresh mode may require considerable power consumption.